1. Field of the Invention
The disclosed embodiments of the present invention relate to a phase detector, and more particularly, to a phase detector with a metastable prevention stage.
2. Description of the Prior Art
For integrated circuits (ICs), path delay of a path is due to a gate delay of each logic gate on the path and a wire delay of the overall wire routing. As IC processes continue to be scaled down, the wire width becomes more and more narrow, which leads to larger resistance. This larger resistance increases the path delay, which will affect signal transmission. Hence, clock skew is an issue which must be taken seriously by designers. In a double-data-rate static dynamic random access memory (SDRAM), if phases of internal signals have difficulties synchronizing with outside signals, the SDRAM will fail to capture data correctly.
A phase-locked loop (PLL) or a delay-locked loop (DLL) can be employed for solving this issue of clock and data synchronization. In both a PLL and a DLL, the most important component is the phase detector. Designers usually adopt circuits free from oscillation for detecting a signal phase to which the PLL/DLL is desired to lock, and then perform full custom design with respect to a specification and process. If the process or specification is changed, however, the current design has to be given up and the full custom design and verification flow must be performed again with respect to the updated process or specification.
In light of this, how to reduce complexity of a phase comparator without affecting the performance thereof has become an urgent issue in the field.